20 miles west of Portland, engineers at an Intel lab are dunking expensive racks of servers "in a clear bath" made of motor oil-like petrochemicals, reports the Oregonian, where the servers "give off a greenish glow as they silently labor away on ordinary computing tasks." Intel's submerged computers operate just as they would on a dry server rack because they're not bathing in water, even though it looks just like it. They're soaking in a synthetic oil that doesn't conduct electricity. So the computers don't short out.

They thrive, in fact, because the fluid absorbs the heat from the hardworking computers much better than air does. It's the same reason a hot pan cools off a lot more quickly if you soak it in water than if you leave it on the stove.

As data centers grow increasingly powerful, the computers are generating so much heat that cooling them uses exorbitant amounts of energy. The cooling systems can use as much electricity as the computers themselves. So Intel and other big tech companies are designing liquid cooling systems that could use far less electricity, hoping to lower data centers' energy costs by as much as a third — and reducing the facilities' climate impact. It's a wholesale change in thinking for data centers, which already account for 2% of all the electricity consumption in the U.S... Skeptics caution that it may be difficult or prohibitively expensive to overhaul existing data centers to adapt to liquid cooling. Advocates of the shift, including Intel, say a transition is imperative to accommodate data centers' growing thirst for power. "It's really starting to come to a head as we're hitting the energy crisis and the need for climate action globally," said Jen Huffstetler, Intel's chief product sustainability officer...

Cooler computers can be packed more tightly together in data centers, since they don't need space for airflow. Computer manufacturers can pack chips together more tightly on the motherboard, enabling more computing power in the same space. And liquid cooling could significantly reduce data centers' environmental and economic costs. Conventional data centers' evaporative cooling systems require tremendous volumes of water and huge amounts of electricity...

Many other tech companies are backing immersion cooling, too. Google, Facebook and Microsoft are all helping fund immersion cooling research at Oregon State... [T]he timing may finally be right for data centers operators to make the shift away from air cooling to something far more efficient. Intel's Huffstetler said she expects to see liquid cooling become widespread in the next three to five years.
The article notes other challenges:

• liquid adds more weight than some buildings' upper floors can support
• Some metals degrade faster in liquid than they do in air.
• And the engineers had to modify the servers by removing their fans — "because they serve no purpose while immersed."

"Kairan Quazi will probably need someone to drive him to work at SpaceX," writes the Los Angeles Times — because "He's only 14." The teen is scheduled to graduate this month from the Santa Clara University School of Engineering before starting a job as a software engineer at the satellite communications and spacecraft manufacturer... The soft-spoken teen said working with Starlink — the satellite internet team at SpaceX — will allow him to be part of something bigger than himself. That is no small feat for someone who has accomplished so much at such a young age...

The youngster jumped from third grade to a community college, with a workload that he felt made sense. "I felt like I was learning at the level that I was meant to learn," said Kairan, who later transferred to Santa Clara University... Kairan's family told BrainGain Magazine that when he was 9, IQ tests showed that his intelligence was in the 99.9th percentile of the general population. Asked if he's a genius, he recalled his parents telling him, "Genius is an action â it requires solving big problems that have a human impact." Once accepted to the engineering school at Santa Clara University as a transfer student, Kairan felt that he had found his freedom to pursue a career path that allowed him to solve those big problems.

While in college, Kairan and his mother made a list of places where he could apply for an internship. Only one company responded. Lama Nachman, director of the Intelligent Systems Research Lab at Intel, took a meeting with 10-year-old Kairan, who expected it to be brief and thought she would give him the customary "try again in a few years," he said. She accepted him. "In a sea of so many 'no's' by Silicon Valley's most vaunted companies, that ONE leader saying yes ... one door opening ... changed everything," Kairan wrote on his LinkedIn page...

Asked what he plans to wear on his first day, Kairan joked in an email that he plans "to show up in head to toe SpaceX merch. I'll be a walking commercial! Joking aside, I'll probably wear jeans and a t-shirt so I can be taken seriously as an engineer."

Next year Intel introduces a new transistor — RibbonFET — and a new way of powering it called "PowerVia."

This so-called "backside power" approach "aims to separate power and I/O wiring, shifting power lines to the back of the wafer," reports Tom's Hardware, which "eliminates any possible interference between the data and power wires and increases logic transistor density." IEEE Spectrum explains this approach "leaves more room for the data interconnects above the silicon," while "the power interconnects can be made larger and therefore less resistive."

And Intel has already done some successful powering tests using it on Intel's current transistors: The resulting cores saw more than a 6 percent frequency boost as well as more compact designs and 30 percent less power loss. Just as important, the tests proved that including backside power doesn't make the chips more costly, less reliable, or more difficult to test for defects. Intel is presenting the details of these tests in Tokyo next week at the IEEE Symposium on VLSI Technology and Circuits...

[C]ores can be made more compact, decreasing the length of interconnects between logic cells, which speeds things up. When the standard logic cells that make up the processor core are laid out on the chip, interconnect congestion keeps them from packing together perfectly, leaving loads of blank space between the cells. With less congestion among the data interconnects, the cells fit together more tightly, with some portions up to 95 percent filled... What's more, the lack of congestion allowed some of the smallest interconnects to spread out a bit, reducing parasitic capacitance that hinders performance...

With the process for PowerVia worked out, the only change Intel will have to make in order to complete its move from Intel 4 to the next node, called 20A, is to the transistor... Success would put Intel ahead of TSMC and Samsung, in offering both nanosheet transistors and backside power.

Intel has announced Intel One Mono, a new font catering to "the needs of developers" with an "expressive" monospace for clarity and legibility" It's easier to read, and available for free, with an open-source font license.

Identifying the typographically underserved low-vision developer audience, Frere-Jones Type designed the Intel One Mono typeface in partnership with the Intel Brand Team and VMLY&R, for maximum legibility to address developers' fatigue and eyestrain and reduce coding errors. A panel of low-vision and legally blind developers provided feedback at each stage of design.
The Linux blog OMG! Ubuntu calls the new font "pretty decent," adding that "Between IBM Plex Mono, Hack, Fira Code, and JetBrains Mono I think we Linux users are spoilt for choice when it comes to open-source monospace fonts that look good and work great.

"Still, there's always room for more, right...?" Better yet, it's not only free to download and use but free to edit, and free to redistribute... Overall, I think Intel One Mono looks great, especially in a text editor (GUI or CLI). There's a noticeable upper and lower margin to the font that in dense text situations allows text to breathe, but in some terminal tools, like Neofetch, the gaps can seem a bit too happy.
The Intel One Mono repository on GitHub includes instructions for activating the font in VSCode and Sublime Text, and lists some extra features accessible in some applications and via CSS:

• There is an option for a raised colon, either applied contextually between numbers or activated generally.

• Superior/superscript and inferior/subscript figures are included via their Unicode codepoints, or you can produce them from the default figures via the sups (Superscript), subs (Subscript), and si (Scientific Inferior) features.

• Fraction numerals are similarly available via the numr (Numerator) and dnom (Denominator) features. A set of premade fractions is also available in the fonts.

At WWDC today, Apple announced a new Mac Pro powered by the M2 Ultra chip. 9to5Mac reports: The chassis design of the machine appears to be the same as the 2019 Intel Mac Pro. The Mac Pro features eight Thunderbolt ports and six PCI slots for modular expansion. The base model config Mac Pro starts at $6999. Mac Pro with M2 Ultra features a 24-core CPU, up to 76-core GPU and 192 GB RAM. It also features two HDMI ports, dual 10-gigabit Ethernet, and a 32-core Neural Engine for machine learning tasks. It also features the latest wireless connectivity with Wi-Fi 6E and Bluetooth 5.3. You'll be able to order the new Mac Pro today via Apple.com.

At WWDC today, Apple announced macOS Sonoma, the latest version of its Mac operating system that includes new features like desktop widgets, aerial screensavers, a new Game mode, and enhancements to apps like Messages and Safari. MacRumors reports: The first feature that Apple detailed was new interactive widgets, which can now be placed right on your desktop. Widgets blend into your desktop wallpaper to not be obtrusive when you're working, and with Continuity you can use the same widgets from your iPhone on your Mac. macOS Sonoma also introduces enhanced video conferencing features, including Presenter Overlay to allow a user to display themselves in front of the content they are sharing. Reactions let users share how they feel within a video session, and Screen Sharing has been improved with a simplified process.

As is usual with macOS updates, Safari is getting numerous new features within Sonoma. There's an update to Private Browsing that provides greater protection from trackers and from people who might have access to the user's device. Profiles within Safari offer a way to separate browsing between topics, like having one for work and one for personal browsing. There's also a new way to create web apps that work like normal apps and let you get to your favorite website faster.

When you're not actively using macOS Sonoma, the new screen savers feature slow-motion videos of various locations worldwide. They shuffle between landscape, Earth, underwater, or cityscape themes, similar to what you'll see on tvOS. For gamers, there's a new Game Mode in macOS Sonoma that delivers an optimized gaming experience with smoother and more consistent frame rates. It dramatically lowers audio latency with AirPods and reduces input latency with game controllers, and it works with any game on Mac. A beta version of macOS Sonoma is now available via the Apple Developer Program, with a public beta launching next month.

As Ars Technica notes, the macOS Sonoma update will only run on a couple generations of Intel Macs. "[I]f you're using anything made before 2018 or anything without an Apple T2 chip in it, you won't be able to run the new OS."

Apple announced the M2 Ultra processor, a new chip for its Mac Studio workstation for professional users. From a report: The chip has 134 transistors and 24 central processing unit (CPU) cores with 20% faster performance. It has up to 76 graphics processing unit (GPU) cores at up to 30% faster performance. Apple made the announcement at its WWDC event today on the Apple campus in Cupertino, California.

The chip will go into the Mac Studio product, which previously used Intel silicon. These are machines like those used by engineers to deliver Saturday Night Live or create blockbuster movies, said Jennifer Munn at Apple. Apple said this completes the transition to Apple silicon. Developers can build new versions of apps at warp speed, with up to 25% faster performance than in the past, Munn said. The 32-core neural engine is 40% faster at AI calculations. It supports 192 gigabytes of unified memory, which is 50% more than M1 Ultra.

Linux computer vendor System76 shared some news in a recent blog post. "We prefer to disable the Intel Management Engine wherever possible to reduce the amount of closed firmware running on System76 hardware. We've resolved a coreboot bug that allows the Intel ME (Management Engine) to once again be disabled."

Phoronix reports that the move will "benefit their latest Intel Core 13th Gen 'Raptor Lake' wares as well as prior generation devices." Intel ME is disabled for their latest Raptor lake laptops and most older platforms with some exceptions like where having a silicon issue with Tiger Lake. System76 has also added a new firmware setup menu option for enabling/disabling UEFI Secure Boot. The motivation here with making it easier to toggle Secure Boot is for allowing Windows 11 support with SB active while running System76 Open Firmware.

ARM has joined the Linux Foundation's Open Programmable Infrastructure project, "a community-driven initiative focused on creating a standards-based open ecosystem for next-generation architectures and frameworks" based on programmable processor technologies like DPUs (Data Processing Units) and IPUs (Infrastructure Processing Units).

From the Linux Foundation's announcement: Launched in June 2021 under the Linux Foundation, the project is focused on utilizing open software and standards, as well as frameworks and toolkits, to enable the rapid adoption of DPUs. Arm joins other premier members including Dell Technologies, F5, Intel, Keysight Technologies, Marvell, Nvidia, Red Hat, Tencent, and ZTE. These member companies work together to create an ecosystem of blueprints and standards to ensure that compliant DPUs work with any server.

DPUs are used today to accelerate networking, security, and storage tasks. In addition to performance benefits, DPUs help improve data center security by providing physical isolation for running infrastructure tasks. DPUs also help to reduce latency and improve performance for applications that require real-time data processing. As DPUs create a logical split between infrastructure compute and client applications, the manageability of workloads within different development and management teams is streamlined.

"Arm has been contributing to the OPI Project for a while now," said Kris Murphy, Chair of the OPI Project Governing Board and Senior Principal Software Engineer at Red Hat. "Now, as a premier member, we are excited that they're bringing their leadership to the Governing Board and expertise to the technical steering committee and working groups. Their participation will help to ensure that the DPU components are optimized for programmable infrastructure solutions."

"Across network, storage, and security applications, DPUs are already proving the power efficiency and capex benefits of specialized processing technology," said Marc Meunier, director of ecosystem development, Infrastructure Line of Business, Arm and member of OPI Governing Board. "As a premier member of the OPI project, we look forward to contributing our expertise in heterogeneous computing and working with other leaders in the industry to create solution blueprints and standards that pave the way for successful deployments."

"The DPU market offers an opportunity for us to change how infrastructure services can be deployed and managed," Arpit Joshipura, General Manager, Networking, Edge, and IoT, the Linux Foundation. "With collaboration across software and hardware vendors representing silicon devices and the entire DPU software stack, the OPI Project is creating an open ecosystem for next generation data centers, private clouds, and edge deployments."

Linux Foundation Europe "has announced the RISC-V Software Ecosystem (RISE) Project to help facilitate more performant, commercial-ready software for the RISC-V processor architecture," reports Phoronix.

"Among the companies joining the RISE Project on their governing board are Andes, Google, Intel, Imagination Technologies, Mediatek, NVIDIA, Qualcomm, Red Hat, Rivos, Samsung, SiFive, T-Head, and Ventana."

It's top goal is "accelerate the development of open source software for RISC-V," according to the official RISE web site. The project's chair says it "brings together leaders with a shared sense of urgency to accelerate the RISC-V software ecosystem readiness in collaboration with RISC-V International." The CEO of RISC-V International, Calista Redmond, said "We are grateful to the thousands of engineers making upstream contributions and to the organizations coming together now to invest in tools and libraries in support of the RISC-V software ecosystem." RISE Project members will contribute financially and provide engineering talent to address specific software deliverables prioritized by the RISE Technical Steering Committee (TSC). RISE is dedicated to enabling a robust software ecosystem specifically for application processors that includes software development tools, virtualization support, language runtimes, Linux distribution integration, and system firmware, working upstream first with existing open source communities in accordance with open source best practices.

"The RISE Project is dedicated to enabling RISC-V in open source tools and libraries (e.g., LLVM, GCC, etc) to speed implementation and time-to-market," said Gabriele Columbro, General Manager of Linux Foundation Europe.
Google's director of engineering on Android said Google was "excited to partner with industry leaders to drive rapid maturity of the RISC-V software ecosystem in support of Android and more."

And the VP of system software at NVIDIA said "NVIDIA's accelerated computing platform — which includes GPUs, DPUs, chiplets, interconnects and software — will support the RISC-V open standard to help drive breakthroughs in data centers, and a wide range of industries, such as automotive, healthcare and robotics."

Arm unveiled its upcoming flagship CPUs for 2024, including the Arm Cortex X4, Cortex A720, and Cortex A520. These chips, built on the Armv9.2 architecture, promise higher performance and improved power efficiency. Arm also introduced a new 'QARMA3 algorithm' for memory security and showcased a potential 14-core mega-chip design for high-performance laptops. Ars Technica reports: Arm claims the big Cortex X3 chip will have 15 percent higher performance than this year's X3 chip, and "40 percent better power efficiency." The company also promises a 20 percent efficiency boost for the A700 series and a 22 percent efficiency boost for the A500. The new chips are all built on the new 'Armv9.2' architecture, which adds a "new QARMA3 algorithm" for Arm's Pointer Authentication memory security feature. Pointer authentication assigns a cryptographic signature to memory pointers and is meant to shut down memory corruption vulnerabilities like buffer overflows by making it harder for unauthenticated programs to create valid memory pointers. This feature has been around for a while, but Arm's new algorithm reduces the CPU overhead of all this extra memory work to just 1 percent of the chip's power, which hopefully will get more manufacturers to enable it.

Arm's SoC recommendations are usually a "1+3+4" design. That's one big X chip, three medium A700 chips, and four A500 chips. This year the company is floating a new layout, though, swapping out two small chips for two medium chips, which would put you at a "1+5+2" configuration. Arm's benchmarks -- which were run on Android 13 -- claim this will get you 27 percent more performance. That's assuming anything can cool and power that for a reasonable amount of time. Arm's blog post also mentions a 1+4+4 chip -- nine cores -- for a flagship smartphone. [...]

Every year with these Arm flagship chip announcements, the company also includes a wild design for a giant mega-chip that usually never gets built. Last year the company's blueprint monster was a design with eight Cortex X3 chips and four A715 cores, which the company claimed would rival an Intel Core i7. The biggest X3-based chip on the market is the Qualcomm Snapdragon 8cx Gen 3, which landed in a few Windows laptops. That was only a four X3/four A715 chip, though. This year's mega chip is a 14-core monster with 10 Cortex X4 chips and four A720 chips, which Arm says is meant for "high-performance laptops." Arm calls the design the company's "most powerful cluster ever built," but will it ever actually be built? Will it ever be more than words on a page?

Rivals such as Nvidia have left Intel far behind. CEO Pat Gelsinger aims to reverse firm's fortunes by vastly expanding its factories. From a report: Pat Gelsinger is keenly aware he must act fast to stop Intel from becoming yet another storied American technology company left in the dust by nimbler competitors. Over the past decade, rivals overtook Intel in making the most advanced chips, graphics-chip maker Nvidia leapfrogged Intel to become America's most valuable semiconductor company, and perennial also-ran AMD has been stealing market share. Intel, by contrast, has faced repeated delays introducing new chips and frustration from would-be customers. "We didn't get into this mud hole because everything was going great," said Gelsinger, who took over as CEO in 2021. "We had some serious issues in terms of leadership, people, methodology, et cetera that we needed to attack."

As he sees it, Intel's problems stem largely from how it botched a transition in how chips are made. Intel came to prominence by both designing circuits and making them in its own factories. Now, chip companies tend to specialize either in circuit design or manufacturing, and Intel hasn't been able to pick up much business making chips designed by other people. So far, the turnaround has been rough. Gelsinger, 62 years old and a devout Christian, said he takes inspiration from the biblical story of Nehemiah, who rebuilt the walls of Jerusalem under attack from his enemies. Last year, he told a Christian group in Singapore: "You'll have your bad days, and you need to have a deep passion to rebuild." Gelsinger's plan is to invest as much as hundreds of billions of dollars into new factories that would make semiconductors for other companies alongside Intel's own chips. Two years in, that contract-manufacturing operation, called a "foundry" business, is bogged down with problems.

Intel will use the "VPU" tech it acquired along with Movidius in 2016 to all models of its forthcoming Meteor Lake client CPUs. From a report: Chipzilla already offers VPUs in some 13th-gen Core silicon. Ahead of the Computex conference in Taiwan, the company briefed The Register on their inclusion in Meteor Lake. Curiously, Intel didn't elucidate the acronym, but has previously said it stands for Vision Processing Unit. Chipzilla is, however, clear about what it does and why it's needed -- and it's more than vision. Intel Veep and general manager of Client AI John Rayfield said dedicated AI silicon is needed because AI is now present in many PC workloads. Video conferences, he said, feature lots of AI enhancing video and making participants sounds great -- and users now just expect that PCs do brilliantly when Zooming or WebExing or Teamising. Games use lots of AI. And GPT-like models, and tools like Stable Diffusion, are already popular on the PC and available as local executables.

CPUs and GPUs do the heavy lifting today, but Rayfield said they'll be overwhelmed by the demands of AI workloads. Shifting that work to the cloud is pricey, and also impractical because buyers want PCs to perform. Meteor Lake therefore gets VPUs and emerges as an SoC that uses Intel's Foveros packaging tech to combine the CPU, GPU, and VPU. The VPU gets to handle "sustained AI and AI offload." CPUs will still be asked to do simple inference jobs with low latency, usually when the cost of doing so is less than the overhead of working with a driver to shunt the workload elsewhere. GPUs will get to do jobs involving performance parallelism and throughput. Other AI-related work will be offloaded to VPUs.

Intel has proposed a potential simplification of the x86 architecture by creating a new x86S architecture that removes certain old features, such as 16-bit and some elements of 32-bit support. A technical note on Intel's developer blog proposes the change, with a 46-page white paper (PDF) providing more details. The Register reports: The result would be a family of processors which boot straight into x86-64 mode. That would mean bypassing the traditional series of transitions -- 16-bit real mode to 32-bit protected mode to 64-bit long mode; or 16-bit mode straight into 64-bit mode -- that chips are obliged to go through as the system starts up. [...] Some of the changes are quite dramatic, although the impact upon how most people use computers today would probably be invisible -- which is undoubtedly the idea.

Intel on Monday provided a handful of new details on a chip for artificial intelligence (AI) computing it plans to introduce in 2025 as it shifts strategy to compete against Nvidia and Advanced Micro Devices. From a report: At a supercomputing conference in Germany on Monday, Intel said its forthcoming "Falcon Shores" chip will have 288 gigabytes of memory and support 8-bit floating point computation. Those technical specifications are important as artificial intelligence models similar to services like ChatGPT have exploded in size, and businesses are looking for more powerful chips to run them.

The details are also among the first to trickle out as Intel carries out a strategy shift to catch up to Nvidia, which leads the market in chips for AI, and AMD, which is expected to challenge Nvidia's position with a chip called the MI300. Intel, by contrast, has essentially no market share after its would-be Nvidia competitor, a chip called Ponte Vecchio, suffered years of delays. Intel on Monday said it has nearly completed shipments for Argonne National Lab's Aurora supercomputer based on Ponte Vecchio, which Intel claims has better performance than Nvidia's latest AI chip, the H100. But Intel's Falcon Shores follow-on chip won't be to market until 2025, when Nvidia will likely have another chip of its own out.

The Top 500 list of the fastest supercomputers in the world was released today, and AMD continues its streak of impressive wins with 121 systems now powered by AMD's silicon -- a year-over-year increase of 29%. From a report: Additionally, AMD continues to hold the #1 spot on the Top 500 with the Frontier supercomputer, while the test and development system based on the same architecture continues to hold the second spot in power efficiency metrics on the Green 500 list. Overall, AMD also powers seven of the top ten systems on the Green 500 list. The AMD-powered Frontier remains the only fully-qualified exascale-class supercomputer on the planet, as the Intel-powered two-exaflop Aurora has still not submitted a benchmark result after years of delays.

In contrast, Frontier is now fully operational and is being used by researchers in a multitude of science workloads. In fact, Frontier continues to improve from tuning -- the system entered the Top 500 list with 1.02 exaflops of performance in June 2022 but has now improved to 1.194 exaflops, a 17% increase. That's an impressive increase from the same 8,699,904 CPU cores it debuted with. For perspective, that extra 92 petaflops of performance from tuning represents the same amount of computational horsepower as the entire Perlmutter system that ranks eighth on the Top 500.

There's shortages of young semiconductor engineers around the world, reports IEEE Spectrum — partially explained by this quote from Intel's director of university research collaboration. "We hear from academics that we're losing EE students to software. But we also need the software. I think it's a totality of 'We need more students in STEM careers.'"

So after America's CHIPS and Science Act "aimed at kick-starting chip manufacturing in the United States," the article notes that universities must attempt bring the U.S. "the qualified workforce needed to run these plants and design the chips." The United States today manufactures just 12 percent of the world's chips, down from 37 percent in 1990, according to a September 2020 report by the Semiconductor Industry Association. Over those decades, experts say, semiconductor and hardware education has stagnated. But for the CHIPS Act to succeed, each fab will need hundreds of skilled engineers and technicians of all stripes, with training ranging from two-year associate degrees to Ph.D.s. Engineering schools in the United States are now racing to produce that talent... There were around 20,000 job openings in the semiconductor industry at the end of 2022, according to Peter Bermel, an electrical and computer engineering professor at Purdue University. "Even if there's limited growth in this field, you'd need a minimum of 50,000 more hires in the next five years. We need to ramp up our efforts really quickly...."

More than being a partner, Intel sees itself as a catalyst for upgrading the higher-education system to produce the workforce it needs, says the company's director of university research collaboration, Gabriela Cruz Thompson. One of the few semiconductor companies still producing most of its wafers in the United States, Intel is expanding its fabs in Arizona, New Mexico, and Oregon. Of the 7,000 jobs created as a result, about 70 percent will be for people with two-year degrees... Since COVID, however, Intel has struggled to find enough operators and technicians with two-year degrees to keep the foundries running. This makes community colleges a crucial piece of the microelectronics workforce puzzle, Thompson says. In Ohio, the company is giving most of its educational funds to technical and community colleges so they can add semiconductor-specific training to existing advanced manufacturing programs. Intel is also asking universities to provide hands-on clean-room experience to community college students.

Samsung and Silicon Labs in Austin are similarly investing in neighboring community colleges and technical schools via scholarships, summer internships, and mentorship programs.
Beyond the deserts of Arizona, chipmakers are eyeing the America's midwest, the article points out (with its "abundance of research universities and technical colleges.")

• Indiana's Purdue launched a new interdisciplinary Semiconductor Degrees Program (building on its Defense Department-funded SCALE program which teaches how to build semiconductors for space), and they've partnered with a local community college to offer training for jobs at the West Lafayette foundry SkyWater.

• The University of Illinois Urbana-Champaign offers an Advanced Systems Design class "which leads senior-year undergrads through every step of making an integrated circuit."

• Intel has pledged $50 million to 80 higher-education institutions in Ohio to "upgrade their curricula, train and hire faculty, and provide equipment," including the funding of a Center for Advanced Semiconductor Fabrication Research and Education to teach semiconductor-related skills to more than just electrical engineering majors.

More than a decade ago engineers at AMD "began toying with a radical idea," remembers the New York Times. Instead of designing one big microprocessor, they "conceived of creating one from smaller chips that would be packaged tightly together to work like one electronic brain."

But with "diminishing returns" from Moore's Law, packaging smaller chips suddenly becomes more important. [Alternate URL here.] As much as 80% of microprocessors will be using these designs by 2027, according to an estimate from the market research firm Yole Group cited by the Times: The concept, sometimes called chiplets, caught on in a big way, with AMD, Apple, Amazon, Tesla, IBM and Intel introducing such products. Chiplets rapidly gained traction because smaller chips are cheaper to make, while bundles of them can top the performance of any single slice of silicon. The strategy, based on advanced packaging technology, has since become an essential tool to enabling progress in semiconductors. And it represents one of the biggest shifts in years for an industry that drives innovations in fields like artificial intelligence, self-driving cars and military hardware. "Packaging is where the action is going to be," said Subramanian Iyer, a professor of electrical and computer engineering at the University of California, Los Angeles, who helped pioneer the chiplet concept. "It's happening because there is actually no other way."

The catch is that such packaging, like making chips themselves, is overwhelmingly dominated by companies in Asia. Although the United States accounts for around 12 percent of global semiconductor production, American companies provide just 3 percent of chip packaging, according to IPC, a trade association. That issue has now landed chiplets in the middle of U.S. industrial policymaking. The CHIPS Act, a $52 billion subsidy package that passed last summer, was seen as President Biden's move to reinvigorate domestic chip making by providing money to build more sophisticated factories called "fabs." But part of it was also aimed at stoking advanced packaging factories in the United States to capture more of that essential process... The Commerce Department is now accepting applications for manufacturing grants from the CHIPS Act, including for chip packaging factories. It is also allocating funding to a research program specifically on advanced packaging...

Some chip packaging companies are moving quickly for the funding. One is Integra Technologies in Wichita, Kan., which announced plans for a $1.8 billion expansion there but said that was contingent on receiving federal subsidies. Amkor Technology, an Arizona packaging service that has most of its operations in Asia, also said it was talking to customers and government officials about a U.S. production presence... Packaging services still need others to supply the substrates that chiplets require to connect to circuit boards and one another... But the United States has no major makers of those substrates, which are primarily produced in Asia and evolved from technologies used in manufacturing circuit boards. Many U.S. companies have also left that business, another worry that industry groups hope will spur federal funding to help board suppliers start making substrates.

In March, Mr. Biden issued a determination that advanced packaging and domestic circuit board production were essential for national security, and announced $50 million in Defense Production Act funding for American and Canadian companies in those fields. Even with such subsidies, assembling all the elements required to reduce U.S. dependence on Asian companies "is a huge challenge," said Andreas Olofsson, who ran a Defense Department research effort in the field before founding a packaging start-up called Zero ASIC. "You don't have suppliers. You don't have a work force. You don't have equipment. You have to sort of start from scratch."

Intel plans a fresh wave of layoffs in the wake of a steep decline in revenue over the last six months. The chipmaker, Oregon's largest corporate employer, blames a weak global economy. From a report: "We are focused on identifying cost reductions and efficiency gains through multiple initiatives, including some business and function-specific workforce reductions in areas across the company," Intel said in a written statement. "These are difficult decisions, and we are committed to treating impacted employees with dignity and respect," Intel said.

Dylan Patel with the technology research firm SemiAnalysis first reported the pending cuts over the weekend. Intel didn't say what else it's cutting, in what areas, or how these layoffs compare to a prior round of job cuts that ended last winter. Intel laid off more than 500 employees in California in job cuts announced last fall, according to filings there with state workforce agencies. It laid off employees in Oregon, too, but didn't make a similar filing here, suggesting that the layoffs represented a smaller percentage of the company's local workforce. Intel employs more than 22,000 at its Washington County campuses.

Last week Linus Torvalds personally cleaned up the x86 memory copy code for Linux 6.4, Phoronix reports — and this week "he's merged more of his own code as he took issue with some of the code merged by Intel engineers as part of their Linear Address Masking enabling." Back during the Linux 6.2 days at the end of last year, Linus rejected the Intel LAM code at the time for various technical issues. Intel then reworked it for Linux 6.4. This time around Linus merged Intel LAM into Linux 6.4 as this new CPU feature for letting user-space store metadata within some bits of pointers without masking it out before use. Intel LAM — like Arm TBI — can be of use to virtual machines, profiling / sanitizers / tagging, and other applications. But this time around there were some less than ideal code that he personally took to sprucing up...

Torvalds reworked around one hundred lines of code for cleaning it up.
It's fun to read Torvalds' commit messages (included in both Phoronix articles). Torvalds begins by writing that the LAM updates "made me unhappy about how 'access_ok()' was done, and it actually turned out to have a couple of small bugs in it too..."