
Intel Demos Its New 'Backside' Power-Delivery Chip Tech (ieee.org) 28
Next year Intel introduces a new transistor — RibbonFET — and a new way of powering it called "PowerVia."
This so-called "backside power" approach "aims to separate power and I/O wiring, shifting power lines to the back of the wafer," reports Tom's Hardware, which "eliminates any possible interference between the data and power wires and increases logic transistor density." IEEE Spectrum explains this approach "leaves more room for the data interconnects above the silicon," while "the power interconnects can be made larger and therefore less resistive."
And Intel has already done some successful powering tests using it on Intel's current transistors: The resulting cores saw more than a 6 percent frequency boost as well as more compact designs and 30 percent less power loss. Just as important, the tests proved that including backside power doesn't make the chips more costly, less reliable, or more difficult to test for defects. Intel is presenting the details of these tests in Tokyo next week at the IEEE Symposium on VLSI Technology and Circuits...
[C]ores can be made more compact, decreasing the length of interconnects between logic cells, which speeds things up. When the standard logic cells that make up the processor core are laid out on the chip, interconnect congestion keeps them from packing together perfectly, leaving loads of blank space between the cells. With less congestion among the data interconnects, the cells fit together more tightly, with some portions up to 95 percent filled... What's more, the lack of congestion allowed some of the smallest interconnects to spread out a bit, reducing parasitic capacitance that hinders performance...
With the process for PowerVia worked out, the only change Intel will have to make in order to complete its move from Intel 4 to the next node, called 20A, is to the transistor... Success would put Intel ahead of TSMC and Samsung, in offering both nanosheet transistors and backside power.
This so-called "backside power" approach "aims to separate power and I/O wiring, shifting power lines to the back of the wafer," reports Tom's Hardware, which "eliminates any possible interference between the data and power wires and increases logic transistor density." IEEE Spectrum explains this approach "leaves more room for the data interconnects above the silicon," while "the power interconnects can be made larger and therefore less resistive."
And Intel has already done some successful powering tests using it on Intel's current transistors: The resulting cores saw more than a 6 percent frequency boost as well as more compact designs and 30 percent less power loss. Just as important, the tests proved that including backside power doesn't make the chips more costly, less reliable, or more difficult to test for defects. Intel is presenting the details of these tests in Tokyo next week at the IEEE Symposium on VLSI Technology and Circuits...
[C]ores can be made more compact, decreasing the length of interconnects between logic cells, which speeds things up. When the standard logic cells that make up the processor core are laid out on the chip, interconnect congestion keeps them from packing together perfectly, leaving loads of blank space between the cells. With less congestion among the data interconnects, the cells fit together more tightly, with some portions up to 95 percent filled... What's more, the lack of congestion allowed some of the smallest interconnects to spread out a bit, reducing parasitic capacitance that hinders performance...
With the process for PowerVia worked out, the only change Intel will have to make in order to complete its move from Intel 4 to the next node, called 20A, is to the transistor... Success would put Intel ahead of TSMC and Samsung, in offering both nanosheet transistors and backside power.